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hys64t128020edl?[2.5/3s/3.7]?b 200-pin ddr2 sdram modules ddr2 sdram so-dimm rohs compliant products internet data sheet rev. 1.1 may 2007
internet data sheet hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules qag_techdoc_rev411 / 3.31 qag / 2007-01-22 2 10312006-i253-v1v0 we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hys64t128020edl?[2.5/3s/3.7]?b revision history: 2007-05, rev. 1.1 page subjects (major chang es since last revision) all adapted internet edition all added product types hys64t128020edl-2.5-b and hys64t128020edl-3s-b previous revision: 2006-10, rev. 1.0 21 added idd currents previous revision: 2006-09, rev. 0.51 all qimonda update previous revision: 2006-04, rev. 0.5
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 3 10312006-i253-v1v0 1 overview this chapter gives an overview of th e 200-pin small-outline ddr2 sdram modules product family and describes its main characteristics. 1.1 features ? 200-pin pc2-6400, pc2-5300 and pc2-4200 ddr2 sdram memory modules. ? 128mx64 module organization, and 64mx16 chip organization ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? 1gb modules built with 1 gbit ddr2 sdrams in pg- tfbga-84-11 chipsize packages ? all speed grades faster than ddr2-400 comply with ddr2-400 timing specifications. ? programmable cas latencies (3, 4, 5 and 6), burst length (8 & 4). ? auto refresh (cbr) and self refresh ? auto refresh for temperatures above 85 c t refi = 3.9 s. ? programmable self refres h rate via emrs2 setting. ? programmable partial array refresh via emrs2 settings. ? dcc enabling via emrs2 setting. ? all inputs and outputs sstl_1.8 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? so-dimm dimensions (nominal ): 30 mm high, 67.60 mm wide ? based on standard reference layouts raw cards 'a' ? rohs compliant products 1) table 1 performance table 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. qag speed code ?2.5 ?3s ?3.7 unit dram speed grade ddr2?800e ddr2?667d ddr2?533c module speed grade pc2?6400e pc2?5300d pc2?4200c cas-rcd-rp latencies 6?6?6 5?5?5 4?4?4 t ck max. clock frequency cl3 f ck3 200 200 200 mhz cl4 f ck4 266 266 266 mhz cl5 f ck5 333 333 266 mhz cl6 f ck6 400 ? ? mhz min. ras-cas-delay t rcd 15 15 15 ns min. row precharge time t rp 15 15 15 ns min. row active time t ras 45 45 45 ns min. row cycle time t rc 60 60 60 ns
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 4 10312006-i253-v1v0 1.2 description the qimonda hys64t128020edl?[2.5/3s/3.7]?b module family are small-outline di mm modules ?so-dimms? with 30 mm height based on ddr2 technology. dimms are available as non-ecc modules in 128mx64 (1gb) in organization and density, intended for mounting into 200-pin connector sockets. the memory array is designed with 1 gbit double-data-rate- two (ddr2) synchronous drams. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer. table 2 ordering information for rohs compliant products table 3 address format table 4 components on modules product type 1) 1) for detailed information regarding product type of qimonda pleas e see chapter "product type nomenclature" of this datasheet. compliance code 2) 2) the compliance code is printed on the module label and descr ibes the speed grade, for example "pc2?6400s?666?12?a0" where 640 0s means small-outline dimm modules with 6.40 gb/sec module bandwidth and "666?12" means column address strobe (cas) latency =6, row column delay (rcd) latency = 6 and row precharge (rp) la tency = 6 using the latest jedec spd revision 1.2 and produced on the raw card "a". description sdram technology pc2-6400 hys64t128020edl-2.5-b 1gb 2rx16 pc2?6400s?666?12?a0 2 ranks, non-ecc 1 gbit (x16) pc2-5300 hys64t128020edl-3s-b 1gb 2rx16 pc2?5300s?555?12?a0 2 ranks, non-ecc 1 gbit (x16) pc2-4200 hys64t128020edl-3.7-b 1gb 2rx16 pc2?4200s?444?12?a0 2 ranks, non-ecc 1 gbit (x16) dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card 1gb 128mx64 2 non-ecc 8 13/3/10 a product type 1)2) 1) green product 2) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. dram components 1) dram density dram organisation hys64t128020edl hyb18t1g160bf 1 gbit 64m x 16
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 5 10312006-i253-v1v0 2 pin configurations and block diagrams 2.1 pin configurations the pin configuration of the small outline ddr2 sdram dimm is listed by function in table 5 (200 pins). the abbreviations used in columns pin type and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 table 5 pin configuration of so-dimm pin no. name pin type buffer type function clock signals 30 ck0 i sstl clock signals 2:0, comple ment clock signals 2:0 the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. 164 ck1 i sstl 32 ck0 isstl 166 ck1 isstl 79 cke0 i sstl clock enable rank 1:0 activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates th e power down mode or the self refresh mode. note: 2 ranks module 80 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 110 s0 isstl chip select rank 1:0 enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . ranks are also called "physica l banks".2 ranks module 115 s1 isstl nc nc ? not connected note: 1-rank module 108 ras isstl row address strobe when sampled at the cross point of the rising edge of ck, and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. 113 cas isstl column address strobe
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 6 10312006-i253-v1v0 109 we isstl write enable address signals 107 ba0 i sstl bank address bus 2:0 selects which ddr2 sdram internal bank of four or eight is activated. 106 ba1 i sstl 85 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc nc sstl less than 1gb ddr2 sdrams 102 a0 i sstl address bus 12:0 during a bank activate comma nd cycle, defines the row address when sampled at the cross-point of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the co lumn address when sampled at the cross point of the risi ng edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the st ate of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. 101 a1 i sstl 100 a2 i sstl 99 a3 i sstl 98 a4 i sstl 97 a5 i sstl 94 a6 i sstl 92 a7 i sstl 93 a8 i sstl 91 a9 i sstl 105 a10 i sstl ap isstl 90 a11 i sstl 89 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies 116 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? not connected note: module based on 512 mbit or smaller dies data signals 5 dq0 i/o sstl data bus 63:0 note: data input/output pins 7 dq1 i/o sstl 17 dq2 i/o sstl 19 dq3 i/o sstl 4 dq4 i/o sstl 6 dq5 i/o sstl 14 dq6 i/o sstl 16 dq7 i/o sstl 23 dq8 i/o sstl 25 dq9 i/o sstl 35 dq10 i/o sstl 37 dq11 i/o sstl pin no. name pin type buffer type function
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 7 10312006-i253-v1v0 20 dq12 i/o sstl data bus 63:0 data input/output pins 22 dq13 i/o sstl 36 dq14 i/o sstl 38 dq15 i/o sstl 43 dq16 i/o sstl 45 dq17 i/o sstl 55 dq18 i/o sstl 57 dq19 i/o sstl 44 dq20 i/o sstl 46 dq21 i/o sstl 56 dq22 i/o sstl 58 dq23 i/o sstl 61 dq24 i/o sstl 63 dq25 i/o sstl 73 dq26 i/o sstl 75 dq27 i/o sstl 62 dq28 i/o sstl 64 dq29 i/o sstl 74 dq30 i/o sstl 76 dq31 i/o sstl 123 dq32 i/o sstl 125 dq33 i/o sstl 135 dq34 i/o sstl 137 dq35 i/o sstl 124 dq36 i/o sstl 126 dq37 i/o sstl 134 dq38 i/o sstl 136 dq39 i/o sstl 141 dq40 i/o sstl 143 dq41 i/o sstl 151 dq42 i/o sstl 153 dq43 i/o sstl 140 dq44 i/o sstl 142 dq45 i/o sstl 152 dq46 i/o sstl 154 dq47 i/o sstl 157 dq48 i/o sstl 159 dq49 i/o sstl 173 dq50 i/o sstl 175 dq51 i/o sstl pin no. name pin type buffer type function
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 8 10312006-i253-v1v0 158 dq52 i/o sstl data bus 63:0 160 dq53 i/o sstl 174 dq54 i/o sstl 176 dq55 i/o sstl 179 dq56 i/o sstl 181 dq57 i/o sstl 189 dq58 i/o sstl 191 dq59 i/o sstl 180 dq60 i/o sstl 182 dq61 i/o sstl 192 dq62 i/o sstl 194 dq63 i/o sstl data strobe signals 13 dqs0 i/o sstl data strobe bus 7:0 the data strobes, associated with one data byte, sourced with data transfers. in writ e mode, the data strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the cross-point of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss and ddr2 sdram mode registers programmed appropriately. 11 dqs0 i/o sstl 31 dqs1 i/o sstl 29 dqs1 i/o sstl 51 dqs2 i/o sstl 49 dqs2 i/o sstl 70 dqs3 i/o sstl 68 dqs3 i/o sstl 131 dqs4 i/o sstl 129 dqs4 i/o sstl 148 dqs5 i/o sstl 146 dqs5 i/o sstl 169 dqs6 i/o sstl 167 dqs6 i/o sstl 188 dqs7 i/o sstl 186 dqs7 i/o sstl data mask signals 10 dm0 i sstl data mask bus 7:0 the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks th e write operation if it is high. in read mode, dm lines have no effect. 26 dm1 i sstl 52 dm2 i sstl 67 dm3 i sstl 130 dm4 i sstl 147 dm5 i sstl 170 dm6 i sstl 185 dm7 i sstl eeprom pin no. name pin type buffer type function
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 9 10312006-i253-v1v0 197 scl i cmos serial bus clock this signal is used to clock data into and out of the spd eeprom and thermal sensor. 195 sda i/o od serial bus data this is a bidirectional pin use to transfer data into and out of the spd eeprom and thermal se nsor. a resistor must be connected from sda to v ddspd on the motherboard to act as a pull-up. 198 sa0 i cmos serial address select bus 2:0 address pins used to select the spd and thermal sensor base address. 200 sa1 i cmos 50 event ood event the optional event pin is reserv ed for use to flag critical module temperature and is used in conjunction with thermal sensor. nc - - not connected not connected on modules wi thout temperature sensors. power supplies 1 v ref ai ? i/o reference voltage reference voltage for the sstl-18 inputs. 199 v ddspd pwr ? eeprom power supply power supplies for serial presence detect, thermal sensor and ground for the module. 81,82,87,88,95 ,96,103,104, 111,112,117,118 v dd pwr ? power supply power supplies for core, i/o and ground for the module. 2,3,8,9,12,15,18,21,24,27,28, 33,34,39,40,41, 42,47,48,53, 54,59,60,65,66, 71,72,77,78, 121,122,127,128, 132,133,138,13 9,144,145,149, 150,155,156,, 161,162,165,17 1,172,177, 178,183,184,18 7,190,193,196 v ss gnd ? ground plane power supplies for core, i/o, serial presence detect, thermal sensor and ground for the module. other pins 114 odt0 i sstl on-die termination control 1:0 119 odt1 i sstl on-die termination control 1 asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. note: 2 rank modules nc nc ? not connected note: 1 rank modules 69,83,84,120,163,168 nc nc ? not connected pins not connected on qimonda so-dimms pin no. name pin type buffer type function
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 10 10312006-i253-v1v0 table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 opera tional states, active lo w and tri-state, and allows multiple devices to share as a wire-or.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 11 10312006-i253-v1v0 figure 1 pin configuration so-dimm (200 pin) - 0 0 4 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 33 $1 $- $1 6 33 $1 $- #+ 6 33 $1 6 33 6 33 $1 $1 6 33 6 33 #+ $1 6 33 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $1 6 33 $- $1 6 33 $1 $13 6 33 $1 .##+% .# 6 $$ ! 6 $$ ! 6 $$ 2!3 6 $$ .#! .# $1 6 33 6 33 $1 $1 6 33 $13 $1 6 33 $1 #+ 6 33 6 33 $1 $1 6 33 $13 $1 6 33 3! 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 6 33 $1 .# % 6%.4 6 33 $1 $1 6 33 $1 3 $1 6 33 6 $$ .# ! ! ! ! ! "! 3 /$ 4 6 $$ 6 33 $1 $- $1 6 33 $1 $1 3 6 33 $1 $1 6 33 #+ $- $1 6 33 $1 $1 3 6 33 $1 3! 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 6 2% & $1 6 33 $13 $1 6 33 $1 $13 6 33 $1 $1 $13 6 33 $1 $1 6 33 $13 $1 6 33 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in $1 6 33 $1 3 $1 6 33 $1 $- 6 33 $1 #+% .# 6 $$ ! 6 $$ ! 6 $$ "! 6 $$ .# 3 .#/ $ 4 $1 6 33 $1 3 $1 6 33 $1 $- $1 6 33 $1 .# $1 3 6 33 $1 $1 6 33 6 33 $1 3$! 6 $$ 30$ 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 0in 6 33 $1 $13 6 33 $1 $1 6 33 .# $1 6 33 6 $$ .# " ! ! ! ! ! ! !0 7% #!3 6 $$ 6 33 $1 $13 6 33 $1 $1 6 33 6 33 $1 $1 6 33 6 33 $13 $1 6 33 $1 $- $1 6 33 3#, 6 33 & 2 / . 4 3 ) $ % " ! # + 3 ) $ % $1 6 33
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 12 10312006-i253-v1v0 3 electrical characteristics 3.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 8 at any time. table 8 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 9 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit note min. max. t case operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where al l dram specification will be supported. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 13 10312006-i253-v1v0 3.2 dc operating conditions table 10 operating conditions table 11 supply voltage levels an d dc operating conditions parameter symbol values unit note min. max. operating temperature (ambient) t opr 0+65 c dram case temperature t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. 2) within the dram component case temperature range all dram specificat ions will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%. storage temperature t stg ? 50 +100 c barometric pressure (operating & storage) pbar +69 +105 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % storage humidity (without condensation) h stg 595% parameter symbol values unit note min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih(dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc )? 0.30 ? v ref ?0.125 v in / output leakage current i l ? 5 ? 5 a 3) 3) input voltage for any connector pin under test of 0 v v in v ddq + 0.3 v; all other pins at 0 v. current is per pin
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 14 10312006-i253-v1v0 3.3 timing characteristics 3.3.1 speed grade definitions table 12 speed grade definition speed grade ?800e ?667d ?533c unit note qag sort name ?2.5 ?3s ?3.7 cas-rcd-rp latencies t ck 6?6?6 5?5?5 4?4?4 parameter symbol min. max. min. max. min. max. ? clock period @ cl = 3 t ck 58 58 5 8 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 38 38 3.758 ns 1)2)3)4) @ cl = 6 t ck 2.5 8 ? ? ? ? ns 1)2)3)4) row active time t ras 45 70k 45 70k 45 70k ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? 60 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? 15 ? 15 ? ns 1)2)3)4) row precharge time t rp 15 ? 15 ? 15 ? ns 1)2)3)4)
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 15 10312006-i253-v1v0 3.3.2 component ac timing parameters table 13 dram component timing parameter by speed grade - ddr2?800 parameter symbol ddr2?800 unit notes 1)2)3)4)5)6) 7)8) min. max. dq output access time from ck / ck t ac ?400 +400 ps 9) cas to cas command delay t ccd 2?nck average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 2500 8000 ps 10)11) cke minimum pulse width ( high and low pulse width) t cke 3?nck 12) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 13)14) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?? ns dq and dm input hold time t dh.base 125 ?? ps 19)20)15) dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg dqs output access time from ck / ck t dqsck ?350 +350 ps 9) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs-dq skew for dqs & associated dq signals t dqsq ?200ps 16) dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 17) dq and dm input setup time t ds.base 50 ?? ps 18)19)20) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 17) dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 17) four activate window for 1kb page size products t faw 35 ? ns 35) four activate window for 2kb page size products t faw 45 ? ns 35) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ ps 21) data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)22) address and control input hold time t ih.base 250 ? ps 23)25) control & address input pulse width for each input t ipw 0.6 ? t ck.avg address and control input setup time t is.base 175 ? ps 24)25) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)22) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)22) mrs command to odt update delay t mod 012ns 35) mode register set command cycle time t mrd 2?nck ocd drive mode output delay t oit 012ns 35)
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 16 10312006-i253-v1v0 dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 26) dq hold skew factor t qhs ?300ps 27) average periodic refresh interval t refi ?7.8 s 28)29) ?3.9 s 29)30) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 31) precharge-all (8 banks) command period t rp t rp +1 t ck ?ns read preamble t rpre 0.9 1.1 t ck.avg 32)33) read postamble t rpst 0.4 0.6 t ck.avg 32)34) active to active command period for 1kb page size products t rrd 7.5 ? ns 35) active to active command period for 2kb page size products t rrd 10 ? ns 35) internal read to precharge command delay t rtp 7.5 ? ns 35) write preamble t wpre 0.35 ? t ck.avg write postamble t wpst 0.4 0.6 t ck.avg write recovery time t wr 15 ? ns 35) internal write to read command delay t wtr 7.5 ? ns 35)36) exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 35) exit self-refresh to read command t xsrd 200 ? nck write command to dqs associated clock edges wl rl ? 1 nck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) parameter symbol ddr2?800 unit notes 1)2)3)4)5)6) 7)8) min. max.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 17 10312006-i253-v1v0 10) input clock jitter spec parameter. these parameters are referr ed to as 'input clock jitter spec parameters' and these param eters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per thei r average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations ). 12) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clocks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 13) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is re ferenced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 3 . 16) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 17) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 18) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a risi ng signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appl ied to the device under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 3 . 19) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 20) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 21) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 22) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are refe renced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 23) input waveform timing is referenced fr om the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 4 . 24) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 4 . 25) these parameters are measured from a command/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 26) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 27) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 28) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 29) 0 c t case 85 c 30) 85 c < t case 95 c 31) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 32) t rpst end point and t rpre begin point are not referenced to a specific voltage leve l but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 2 shows a method to calculate these point s when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 18 10312006-i253-v1v0 table 14 dram component timing parameter by speed grade - ddr2?667 33) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 34) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 35) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are met. th is means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input clock jitter specificatio ns are met, precharge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 36) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. parameter symbol ddr2?667 unit notes 1)2)3)4)5)6) 7)8) min. max. dq output access time from ck / ck t ac ?450 +450 ps 9) cas to cas command delay t ccd 2?nck average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 3000 8000 ps cke minimum pulse width ( high and low pulse width) t cke 3?nck 12) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 13)14) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?? ns dq and dm input hold time t dh.base 175 ?? ps 19)20)15) dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg dqs output access time from ck / ck t dqsck ?400 +400 ps 9) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs-dq skew for dqs & associated dq signals t dqsq ?240ps 16) dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 17) dq and dm input setup time t ds.base 100 ?? ps 18)19)20) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 17) dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 17) four activate window for 1kb page size products t faw 37.5 ? ns 35) four activate window for 2kb page size products t faw 50 ? ns 35) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ ps 21) data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)22) address and control input hold time t ih.base 275 ? ps 25)23)
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 19 10312006-i253-v1v0 control & address input pulse width for each input t ipw 0.6 ? t ck.avg address and control input setup time t is.base 200 ? ps 24)25) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)22) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)22) mrs command to odt update delay t mod 012ns 35) mode register set command cycle time t mrd 2?nck ocd drive mode output delay t oit 012ns 35) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 26) dq hold skew factor t qhs ?340ps 27) average periodic refresh interval t refi ?7.8 s 28)29) ?3.9 s 29)30) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 31) precharge-all (8 banks) command period t rp t rp +1 t ck ?ns read preamble t rpre 0.9 1.1 t ck.avg 32)33) read postamble t rpst 0.4 0.6 t ck.avg 32)34) active to active command period for 1kb page size products t rrd 7.5 ? ns 35) active to active command period for 2kb page size products t rrd 10 ? ns 35) internal read to precharge command delay t rtp 7.5 ? ns 35) write preamble t wpre 0.35 ? t ck.avg write postamble t wpst 0.4 0.6 t ck.avg write recovery time t wr 15 ? ns 35) internal write to read command delay t wtr 7.5 ? ns 35)36) exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 35) exit self-refresh to read command t xsrd 200 ? nck write command to dqs associated clock edges wl rl?1 nck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . parameter symbol ddr2?667 unit notes 1)2)3)4)5)6) 7)8) min. max.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 20 10312006-i253-v1v0 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are referr ed to as 'input clock jitter spec parameters' and these param eters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per thei r average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations ). 12) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clocks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 13) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is re ferenced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 3 . 16) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 17) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 18) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a risi ng signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appl ied to the device under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 3 . 19) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 20) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 21) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 22) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are refe renced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 23) input waveform timing is referenced fr om the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 4 . 24) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 4 . 25) these parameters are measured from a command/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 26) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 27) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 21 10312006-i253-v1v0 figure 2 method for calculating transitions and endpoint figure 3 differential input waveform timing - t ds and t ds 28) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 29) 0 c t case 85 c 30) 85 c < t case 95 c 31) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 32) t rpst end point and t rpre begin point are not referenced to a specific voltage leve l but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 2 shows a method to calculate these point s when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. 33) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 34) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 35) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are met. th is means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input clock jitter specificatio ns are met, precharge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 36) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. w+= w53 6 7 hq gsr l q w 7 7 92 +[p 9 92 +[p 9 92 / [p 9 92 / [p 9 w/= w5 35( ehj l q srlqw 7 7 977 [p9 977 [p9 977 [ p9 977 [p9 w/= w53 5 ( ehjl qsrl qw 7 7 w+=w53 6 7 hq gsrl qw 7 7 w' 6 9 '' 4 9 ,+d f pl q 9 ,+g f pl q 6 2%&dc 9 ,/ g f pd [ 9 ,/ d f pd [ 9 66 '4 6 '46 w'+ w'6 w'+
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 22 10312006-i253-v1v0 figure 4 differential input waveform timing - t ls and t lh table 15 dram component timing parameter by speed grade - ddr2?533 parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max. dq output access time from ck / ck t ac ?500 +500 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 9) dq and dm input hold time (differential data strobe) t dh (base) 225 ?? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ?300ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) w,6 9 '' 4 9 ,+ d f plq 9 ,+ g f plq 9 5()gf 9 ,/ g f pd [ 9 ,/ d f pd [ 9 66 &. &. w, + w, 6 w, +
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 23 10312006-i253-v1v0 dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck four activate window period t faw 37.5 ? ns four activate window period t faw 50 ? ns 13) clock half period t hp min. ( t cl, t ch ) 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 375 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mrs command to odt update delay t mod 012ns mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs ?400ps average periodic refresh interval t refi ?7.8 s 14)15) average periodic refresh interval t refi ?3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 17) precharge-all (8 banks) command period t rp t rp +1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) active bank a to active bank b command period t rrd 10 ? ns 16)22) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns internal write to read command delay t wtr 7.5 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 21) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 24 10312006-i253-v1v0 exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck write recovery time for write with auto- precharge wr t wr / t ck t ck 22) 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the act ual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 2 ?ordering information for rohs compliant products? on page 4 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. 22) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max.
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 25 10312006-i253-v1v0 3.3.3 odt ac electrical characteristics this chapter describes the odt ac electrical characteristics. table 16 odt ac characteristics and operating conditions for ddr2-667 & ddr2-800 table 17 odt ac characteristics and operating conditions for ddr2-533 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 n ck 1) 1) new units, ?t ck.avg ? and ? n ck ?, are introduced in ddr2-667 and ddr2-800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ? n ck ? represents one clock cycle of the input clock, count ing the actual clock edges. note that in ddr2-400 and ddr2-533, ? t ck ? is used for both concepts. example: t xp = 2 [ n ck ] means; if power down exit is registered at t m , an active command may be registered at t m + 2, even if ( t m + 2 - t m ) is 2 x t ck.avg + t err.2per(min) . t aon odt turn-on t ac.min t ac.max +0.7ns ns 1)2) 2) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-667/800, t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max +1 ns ns 1) t aofd odt turn-off delay 2.5 2.5 n ck 1) t aof odt turn-off t ac.min t ac.max +0.6ns ns 1)3) 3) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-667/800, if t ck(avg) = 3 ns is assumed, t aofd is 1.5 ns (= 0.5 x 3 ns) after the second trai ling clock edge counting from the clock edge t hat registered a first odt low and by coun ting the actual input clock edges. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max +1ns ns 1) t anpd odt to power down mode entry latency 3 ? n ck 1) t axpd odt power down exit latency 8 ? n ck 1) symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-400/533, t aond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 26 10312006-i253-v1v0 3.4 i dd specifications and conditions list of tables defining i dd specifications and conditions. ? table 18 ? i dd measurement conditions? on page 26 ? table 19 ?definitions for i dd ? on page 27 table 18 i dd measurement conditions 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-400/533, t aofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. parameter symbol note 1)2) 3)4)5) operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, databus inputs are switching. i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating. i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n active power-down current all banks open; t ck = t ck.min , cke is low; other control and addres s inputs are stable, data bus inputs are floating. mrs a12 bit is se t to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) operating current - burst read all banks open; continuous burst re ads; bl = 4; al = 0, cl = cl min ; t ck = t ckmin ; t ras = t rasmax ; t rp = t rpmin ; cke is high, cs is high between valid co mmands; address inputs are switching; data bus inputs are switching; i out = 0ma. i dd4r 6) operating current - burst write all banks open; continuous burst wr ites; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus in puts are switching; i dd4w
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 27 10312006-i253-v1v0 table 19 definitions for i dd burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ck.min. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 6) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after t he device is properly initialized and i dd parameter are specified with odt disabled. 3) definitions for i dd see table 19 4) for two rank modules: all active current measurements in the same i dd current mode. the other rank is in i dd2p precharge power-down mode 5) for details and notes see the relevant qimonda component data sheet 6) i dd1 , i dd4r and i dd7 current measurements are defined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabled using an emrs(1) (extended m ode register command) by setting a12 bit to high. parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between high and low ever y other clock (once per 2 cycles) for address and control signals, and inputs changing between high and lo w every other data transfer (once per cycle) for dq signals not including mask or strobes parameter symbol note 1)2) 3)4)5)
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 28 10312006-i253-v1v0 table 20 i dd specification for hys64t128020edl?[2.5/3s/3.7]?b product type hys64t128020edl?2.5?b hys64t 128020edl?3s?b hys64t128020edl?3.7?b units note 1) 1) calculated values from component data. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 1 gb 1 gb 1 gb 64 64 64 2 ranks2 ranks2 ranks ?2.5 ?3s ?3.7 i dd0 648 588 548 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 688 628 568 ma 2) i dd2n 560 520 440 ma 3) 3) both ranks are in the same i dd current mode i dd2p 96 96 96 ma 3) i dd2q 520 480 400 ma 3) i dd3n 720 560 480 ma 3) i dd3p_0 (fast) 384 360 304 ma 3)4) 4) fast: mrs(12)=0 i dd3p_1 (slow) 120 120 120 ma 3)5) 5) slow: mrs(12)=1 i dd4r 1008 868 748 ma 2) i dd4w 1008 868 748 ma 2) i dd5b 948 888 848 ma 2) i dd5d 104 104 104 ma 3)6) 6) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 64 64 64 ma 3)6) i dd7 1408 1248 1168 ma 2)
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 29 10312006-i253-v1v0 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 21 ?pc2?6400?666? on page 29 ? table 22 ?pc2?5300?555? on page 33 ? table 23 ?pc2?4200?444? on page 37 table 21 pc2?6400?666 product type hys64t128020edl?2.5?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?6400s?666 jedec spd revision rev. 1.2 byte# description hex 0 programmed spd bytes in eeprom 80 1 total number of bytes in eeprom 08 2 memory type (ddr2) 08 3 number of row addresses 0d 4 number of column addresses 0a 5 dimm rank and stacking information 61 6 data width 40 7 not used 00 8 interface voltage level 05 9 t ck @ cl max (byte 18) [ns] 25 10 t ac sdram @ cl max (byte 18) [ns] 40 11 error correction support (non-ecc, ecc) 00 12 refresh rate and type 82 13 primary sdram width 10 14 error checking sdram width 00 15 not used 00 16 burst length supported 0c 17 number of banks on sdram device 08 18 supported cas latencies 70 19 dimm mechanical characteristics 01
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 30 10312006-i253-v1v0 20 dimm type information 04 21 dimm attributes 00 22 component attributes 07 23 t ck @ cl max -1 (byte 18) [ns] 30 24 t ac sdram @ cl max -1 [ns] 45 25 t ck @ cl max -2 (byte 18) [ns] 3d 26 t ac sdram @ cl max -2 [ns] 50 27 t rp.min [ns] 3c 28 t rrd.min [ns] 28 29 t rcd.min [ns] 3c 30 t ras.min [ns] 2d 31 module density per rank 80 32 t as.min and t cs.min [ns] 17 33 t ah.min and t ch.min [ns] 25 34 t ds.min [ns] 05 35 t dh.min [ns] 12 36 t wr.min [ns] 3c 37 t wtr.min [ns] 1e 38 t rtp.min [ns] 1e 39 analysis characteristics 00 40 t rc and t rfc extension 06 41 t rc.min [ns] 3c 42 t rfc.min [ns] 7f 43 t ck.max [ns] 80 44 t dqsq.max [ns] 14 45 t qhs.max [ns] 1e 46 pll relock time 00 47 t case.max delta / ? t 4r4w delta 5f 48 psi(t-a) dram 58 49 ? t 0 (dt0) 53 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 3b 51 ? t 2p (dt2p) 27 52 ? t 3n (dt3n) 2a product type hys64t128020edl?2.5?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?6400s?666 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 31 10312006-i253-v1v0 53 ? t 3p.fast (dt3p fast) 43 54 ? t 3p.slow (dt3p slow) 1e 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 54 56 ? t 5b (dt5b) 22 57 ? t 7 (dt7) 42 58 psi(ca) pll 00 59 psi(ca) reg 00 60 ? t pll (dtpll) 00 61 ? t reg (dtreg) / toggle rate 00 62 spd revision 12 63 checksum of bytes 0-62 22 64 manufacturer?s jedec id code (1) 7f 65 manufacturer?s jedec id code (2) 7f 66 manufacturer?s jedec id code (3) 7f 67 manufacturer?s jedec id code (4) 7f 68 manufacturer?s jedec id code (5) 7f 69 manufacturer?s jedec id code (6) 51 70 manufacturer?s jedec id code (7) 00 71 manufacturer?s jedec id code (8) 00 72 module manufacturer location xx 73 product type, char 1 36 74 product type, char 2 34 75 product type, char 3 54 76 product type, char 4 31 77 product type, char 5 32 78 product type, char 6 38 79 product type, char 7 30 80 product type, char 8 32 81 product type, char 9 30 82 product type, char 10 45 83 product type, char 11 44 84 product type, char 12 4c 85 product type, char 13 32 product type hys64t128020edl?2.5?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?6400s?666 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 32 10312006-i253-v1v0 86 product type, char 14 2e 87 product type, char 15 35 88 product type, char 16 42 89 product type, char 17 20 90 product type, char 18 20 91 module revision code 0x 92 test program revision code xx 93 module manufacturing date year xx 94 module manufacturing date week xx 95 - 98 module serial number xx 99 - 127 not used 00 128 - 255 blank for customer use ff product type hys64t128020edl?2.5?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?6400s?666 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 33 10312006-i253-v1v0 table 22 pc2?5300?555 product type hys64t128020edl?3s?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?5300s?444 jedec spd revision rev. 1.2 byte# description hex 0 programmed spd bytes in eeprom 80 1 total number of bytes in eeprom 08 2 memory type (ddr2) 08 3 number of row addresses 0d 4 number of column addresses 0a 5 dimm rank and stacking information 61 6 data width 40 7 not used 00 8 interface voltage level 05 9 t ck @ cl max (byte 18) [ns] 30 10 t ac sdram @ cl max (byte 18) [ns] 45 11 error correction support (non-ecc, ecc) 00 12 refresh rate and type 82 13 primary sdram width 10 14 error checking sdram width 00 15 not used 00 16 burst length supported 0c 17 number of banks on sdram device 08 18 supported cas latencies 38 19 dimm mechanical characteristics 01 20 dimm type information 04 21 dimm attributes 00 22 component attributes 07 23 t ck @ cl max -1 (byte 18) [ns] 30 24 t ac sdram @ cl max -1 [ns] 45 25 t ck @ cl max -2 (byte 18) [ns] 50 26 t ac sdram @ cl max -2 [ns] 60 27 t rp.min [ns] 30 28 t rrd.min [ns] 28 29 t rcd.min [ns] 30
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 34 10312006-i253-v1v0 30 t ras.min [ns] 2d 31 module density per rank 80 32 t as.min and t cs.min [ns] 20 33 t ah.min and t ch.min [ns] 27 34 t ds.min [ns] 10 35 t dh.min [ns] 17 36 t wr.min [ns] 3c 37 t wtr.min [ns] 1e 38 t rtp.min [ns] 1e 39 analysis characteristics 00 40 t rc and t rfc extension 06 41 t rc.min [ns] 39 42 t rfc.min [ns] 7f 43 t ck.max [ns] 80 44 t dqsq.max [ns] 18 45 t qhs.max [ns] 22 46 pll relock time 00 47 t case.max delta / ? t 4r4w delta 5d 48 psi(t-a) dram 58 49 ? t 0 (dt0) 47 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 32 51 ? t 2p (dt2p) 27 52 ? t 3n (dt3n) 24 53 ? t 3p.fast (dt3p fast) 39 54 ? t 3p.slow (dt3p slow) 1e 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 48 56 ? t 5b (dt5b) 21 57 ? t 7 (dt7) 37 58 psi(ca) pll 00 59 psi(ca) reg 00 60 ? t pll (dtpll) 00 61 ? t reg (dtreg) / toggle rate 00 62 spd revision 12 product type hys64t128020edl?3s?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?5300s?444 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 35 10312006-i253-v1v0 63 checksum of bytes 0-62 e6 64 manufacturer?s jedec id code (1) 7f 65 manufacturer?s jedec id code (2) 7f 66 manufacturer?s jedec id code (3) 7f 67 manufacturer?s jedec id code (4) 7f 68 manufacturer?s jedec id code (5) 7f 69 manufacturer?s jedec id code (6) 51 70 manufacturer?s jedec id code (7) 00 71 manufacturer?s jedec id code (8) 00 72 module manufacturer location xx 73 product type, char 1 36 74 product type, char 2 34 75 product type, char 3 54 76 product type, char 4 31 77 product type, char 5 32 78 product type, char 6 38 79 product type, char 7 30 80 product type, char 8 32 81 product type, char 9 30 82 product type, char 10 45 83 product type, char 11 44 84 product type, char 12 4c 85 product type, char 13 33 86 product type, char 14 53 87 product type, char 15 42 88 product type, char 16 20 89 product type, char 17 20 90 product type, char 18 20 91 module revision code 0x 92 test program revision code xx 93 module manufacturing date year xx 94 module manufacturing date week xx 95 - 98 module serial number xx product type hys64t128020edl?3s?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?5300s?444 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 36 10312006-i253-v1v0 99 - 127 not used 00 128 - 255 blank for customer use ff product type hys64t128020edl?3s?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?5300s?444 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 37 10312006-i253-v1v0 table 23 pc2?4200?444 product type hys64t128020edl?3.7?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?4200s?444 jedec spd revision rev. 1.2 byte# description hex 0 programmed spd bytes in eeprom 80 1 total number of bytes in eeprom 08 2 memory type (ddr2) 08 3 number of row addresses 0d 4 number of column addresses 0a 5 dimm rank and stacking information 61 6 data width 40 7 not used 00 8 interface voltage level 05 9 t ck @ cl max (byte 18) [ns] 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 11 error correction support (non-ecc, ecc) 00 12 refresh rate and type 82 13 primary sdram width 10 14 error checking sdram width 00 15 not used 00 16 burst length supported 0c 17 number of banks on sdram device 08 18 supported cas latencies 38 19 dimm mechanical characteristics 00 20 dimm type information 04 21 dimm attributes 00 22 component attributes 07 23 t ck @ cl max -1 (byte 18) [ns] 3d 24 t ac sdram @ cl max -1 [ns] 50 25 t ck @ cl max -2 (byte 18) [ns] 50 26 t ac sdram @ cl max -2 [ns] 60 27 t rp.min [ns] 3c 28 t rrd.min [ns] 28 29 t rcd.min [ns] 3c
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 38 10312006-i253-v1v0 30 t ras.min [ns] 2d 31 module density per rank 80 32 t as.min and t cs.min [ns] 25 33 t ah.min and t ch.min [ns] 37 34 t ds.min [ns] 10 35 t dh.min [ns] 22 36 t wr.min [ns] 3c 37 t wtr.min [ns] 1e 38 t rtp.min [ns] 1e 39 analysis characteristics 00 40 t rc and t rfc extension 06 41 t rc.min [ns] 3c 42 t rfc.min [ns] 7f 43 t ck.max [ns] 80 44 t dqsq.max [ns] 1e 45 t qhs.max [ns] 28 46 pll relock time 00 47 t case.max delta / ? t 4r4w delta 59 48 psi(t-a) dram 60 49 ? t 0 (dt0) 3f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 2a 51 ? t 2p (dt2p) 2b 52 ? t 3n (dt3n) 20 53 ? t 3p.fast (dt3p fast) 35 54 ? t 3p.slow (dt3p slow) 21 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 40 56 ? t 5b (dt5b) 22 57 ? t 7 (dt7) 31 58 psi(ca) pll 00 59 psi(ca) reg 00 60 ? t pll (dtpll) 00 61 ? t reg (dtreg) / toggle rate 00 62 spd revision 12 product type hys64t128020edl?3.7?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?4200s?444 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 39 10312006-i253-v1v0 63 checksum of bytes 0-62 42 64 manufacturer?s jedec id code (1) 7f 65 manufacturer?s jedec id code (2) 7f 66 manufacturer?s jedec id code (3) 7f 67 manufacturer?s jedec id code (4) 7f 68 manufacturer?s jedec id code (5) 7f 69 manufacturer?s jedec id code (6) 51 70 manufacturer?s jedec id code (7) 00 71 manufacturer?s jedec id code (8) 00 72 module manufacturer location xx 73 product type, char 1 36 74 product type, char 2 34 75 product type, char 3 54 76 product type, char 4 31 77 product type, char 5 32 78 product type, char 6 38 79 product type, char 7 30 80 product type, char 8 32 81 product type, char 9 30 82 product type, char 10 45 83 product type, char 11 44 84 product type, char 12 4c 85 product type, char 13 33 86 product type, char 14 2e 87 product type, char 15 37 88 product type, char 16 42 89 product type, char 17 20 90 product type, char 18 20 91 module revision code 3x 92 test program revision code xx 93 module manufacturing date year xx 94 module manufacturing date week xx 95 - 98 module serial number xx product type hys64t128020edl?3.7?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?4200s?444 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 40 10312006-i253-v1v0 99 - 127 not used 00 128 - 255 blank for customer use ff product type hys64t128020edl?3.7?b organization 1 gbyte 64 2 ranks ( 16) label code pc2?4200s?444 jedec spd revision rev. 1.2 byte# description hex
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 41 10312006-i253-v1v0 5 package outlines figure 5 package outline raw ca rd a lg-dim-200-31 notes 1. thermal sensor (optional) 2. spd or combidevice (if used then no thermal sensor needed) ' , $ ? ? ? ? ? ? ? ? ? ? - ) . ? ? $ e t a i l o f c o n t a c t s - ! 8 ? ? ? $ r a w i n g a c c o r d i n g t o ) 3 / ' e n e r a l t o l e r a n c e s ? $ i m e n s i o n s i n m m
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 42 10312006-i253-v1v0 6 product type nomenclature qimonda?s nomenclature uses simple coding combined with some proprietary coding. table 24 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 25 and for components in table 26 . table 24 nomenclature fields and examples table 25 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64/128 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512/1g 16 0 a c ?5 field description values coding 1 qimonda module prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 43 10312006-i253-v1v0 table 26 ddr2 dram nomenclature 10 speed grade ?19f pc2?8500 6?6?6 ?1.9 pc2?8500 7?7?7 ?25f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?19f pc2?8500 6?6?6 ?1.9 pc2?8500 7?7?7 ?25f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 field description values coding
hys64t128020edl?[2.5/3s/3.7]?b small outlined ddr2 sdram modules internet data sheet rev. 1.1, 2007-05 44 10312006-i253-v1v0 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configurations and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 component ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 i dd specifications and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
edition 2007-05 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a gua rantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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